A Very Large Scale Integration (VLSI) chip is generally composed of a silicon die having an integrated circuit fabricated thereon, a package for housing the silicon die that can be made of ceramic, organic or other types of chip carrier packages, and various means of electronic connection to the silicon die that extends to the exterior of the package for connection in an electronic system. Transistors and other circuit components reside on the silicon die in printed form and require power and signal connection extending to the exterior of the package. These connections would typically be coupled to a printed circuit board for further integration with other electronic components. The component features of the silicon die are extremely small, in the order of 0.1 to 1 micro-meter (Micron), whereas the features in the printed circuit board are in the order of 0.1 to 1 millimeter (mm). The connection configurations of a chip package bridge this large scaling gap by providing power and signal connections between the silicon die and the printed circuit board.
Referring to FIG. 1A, one configuration of a conventional chip package 100 is shown. The VLSI chip 102 is shown mounted on a ceramic base 104 and is connected via bond wires 106 to connection pins 108 through pin circuitry 112 of the chip package 100. The ceramic base 104 is coupled to the chip package 100 to dissipate heat from the VLSI chip 102 into the ambient outside the chip package 100. Also, the bond wires 106 are often a tenuous connection in the package 100 and are subject to defects. The connection pins 108 are configured to mount on a circuit board for further connection to other components.
Referring now to FIG. 1B, a top view of the chip package 100 is shown where bond wires 106 connect bonding pads 110 to the pin circuitry 112. As a result of manufacturing constraints, a design utilizing bond wires 106 such as in the chip package 100 have a limited access to pads 110 such that the pads 110 reside only on the periphery of the VLSI chip 102. Thus, the number of power and signal connections are greatly limited by the number of pads that can be accessed around the periphery of VLSI chip 102.
A second configuration of a conventional chip package 114 is shown in FIG. 1C. This configuration is known in the art as a "C-4 mount." In this configuration, the VLSI chip 116 is connected to the pin circuitry 118 via soldering bumps 120 located on the bottom surface of the VLSI chip 116. Here, the chip is inverted, or flipped, so that connections can be made to pins 108. As can be seen in FIG. 1D, this configuration allows a greater number of landing pads 122 on the surface of the VLSI chip 116 since the design is not limited to placing the landing pads on the periphery of the surface of VLSI 116. This solves the need for the increasing number of connections required to VLSI chips, particularly, microprocessors that have ever increasing demands for more signal connection and more power. An increase in the number of connections to the landing pads 122 allows for more signal lines and power lines to the VLSI chip. Also, the bond wires used in the design of FIG. 1 are eliminated. Details regarding one method of solder connections used in joining integrated semiconductor devices are found in related application "Multilayer Solder Interconnection Structure" of Mashimoto et al. cited above. Demands for higher power and more signals, however, continue to increase.
With each new generation, of VLSI chips continue to grow in complexity, performance and power consumption. As a result, the current demands for the chips has also increased. One of the biggest challenges for future generations of chips is managing the chip's power consumption. Presently, the power consumption of a typical microprocessor is between 1 and 60 watts. As new generations of microprocessors are developed, however, the power demands are expected to increase into the hundreds or even thousands of watts as complexity of the chip increases and as better chip performance is demanded. Also, as more complicated microprocessors are developed, more transistors are used, the size of the silicon die grows and the signal frequency greatly increases. The net effect is that the power and current demands will continue to be major concerns in chip design.
One modern solution to manage increased power demand is voltage scaling. Voltage scaling is the process of reducing the voltage level of signals located inside and outside the VLSI chips so that less power is demanded. Power has a quadratic relationship to voltage where power is proportional to the square of the voltage. Hence, if the supply voltage is reduced by half, the power is reduced by one-fourth, giving a dramatic decrease in the power demand. Voltage scaling continues to be practiced in modern chip designs. For example, in the 1980's, the typical power supply voltage was 5 volts. Later in the 1990's, the average supply voltage was reduced to 3.3 volts. More modern designs have reduced the supply voltage to as low as 2.5 volts and even 1.8 volts. Voltage scaling, however, has its limits and the continuing increase in power and current demands are still inevitable.
Unlike power, current is linearly proportional to voltage. Therefore, if the supply voltage is reduced by half, the current is also reduced by half. Hence, voltage scaling only reduces supply currents by the same rate as reduction in voltage. Referring to FIG. 2, a logarithmic graph shows how microprocessor current demands have changed over the years. For example, the Intel 386 microprocessor had a current demand of less than 0.2 amperes. In 1989, the Intel 486 microprocessor had twice the demand of the 386 microprocessor of approximately 0.4 amperes. Still further, the Pentium processor, available in 1983, had a much higher power demand of around 3 amperes. At this rate, according to the projected graph of FIG. 2, as time goes on, the current demand for microprocessors will greatly increase into the hundreds and even thousands of amperes.
As mentioned above, the present designs of chip packages supply power and ground currents to the silicon die using package pins, bond wires, solder bumps and landing pads on the die. As current and signal demands increase, the number of package pins and VLSI landing pads will increase dramatically in order to meet the demand of the current supplies and signal connections. Conventional technology can allow for around 100 milli-amperes for each landing pad on the die without sacrificing performance of the chip. As a result, as complexity, performance and power demands increase, a larger number of landing pads and pins will be required that consume a great amount of space on the silicon die. All of these factors increase the cost of producing the chip.
In conventional systems, supply current and ground current sources are connected to the chip packages in the same fashion as communication signals. The supply current and ground current connections supply the energy needed for the VLSI chip's operation. Unlike the signal connection, the supply current and ground current sources (Vcc, Vss, respectively ) have very few connections to the chip. The communication lines, however, carry a very low amount of current and are greater in number. As power demand increases, however, a larger number of supply and ground current connections will be needed in order to keep up with the higher demanding VLSI chips. A major problem is that for every supply and signal there exists one pin on the package, one bond wire or solder connection to the die and one landing pad on the die. As complexity increases, the chip package becomes crowded with electrical connections. One solution would be to reduce the number of pins in the package. Unfortunately, this would increase the resistance in the signal path, thereby increasing the voltage drop in accordance with Ohm's law (V=IR). The result is supplying reduced voltage to the chip. On the other hand, if the number of pins is increased, the result is a larger package for the silicon die, which ultimately increases the cost of the chip. Typically, these two design parameters are balanced in determining the proper number of power and ground paths for a given application. It would be useful to provide a supply current directly to the chip to eliminate the need for multiple pins to the chip using conventional electrical connections. As will be seen, one embodiment of the present invention solves this problem in a simple and elegant manner.
With ever increasing power demands in next generation microprocessors and other VLSI's, heat dissipation is becoming another design concern. FIG. 3 illustrates a conventional solution to power dissipation in a VLSI chip package 300. The overall package 300 is similar to that of FIG. 1 with the addition of cooling fins 302 mounted on base 304. The base 304 is typically made up of ceramic material for rapid heat dissipation and can also be constructed of organic or conductive material to help dissipate the heat through the cooling fins 302. The VLSI chip 306 generates heat which is dissipated through the solder connections 308 or other connections that transfer heat to the base 304 for eventual dissipation through the cooling fins 302. The package is typically mounted to a mother board 310 via power and ground pins 312. The cooling fins 302 are usually exposed to the ambient within a system such a computer chassis that may further provide fans and other cooling means to help dissipate the heat generated by the components in the system. Other heat generating components in a computer system pose further problems in dissipating heat since, as a whole, the collective components increase the ambient temperature within the computer system. The demand for more compact systems such as laptop computers further complicates the heat dissipation problem by locating the heat generating components together closely in the system with often inadequate means to dissipate heat.
A modern method and more aggressive cooling technique is illustrated in FIG. 4 having cooling fans 400 located closely to the cooling fins 402 and mounted on the chip packages 404. Like the design of FIG. 3, the chip packages 404 are still mounted to the mother board 406 via power and ground pins 408 for interconnection to the rest of the system (not shown). The cooling fins can be mounted directly on the chip package and are capable of dissipating a large amount of heat from the VLSI chip packages 404. Power converters 410 are usually mounted in close proximity to the chip packages 404 for convenient access to the chip packages 404. Although effective, even this modern cooling method has its limits and will eventually become obsolete as power demands for VLSI chips increase.
It will be appreciated by those skilled in the art that the rate of cooling is directly proportional to the difference in temperature, Newton's law. Since the inside of a computer system, for example, is warm as a result of the collective heat generating components, it will be useful to somehow expose the VLSI chips to the ambient of lower temperature for more efficient heat dissipation.
One technique used in the entertainment electronics industry is to expose large heat generating transistors to the backside of, for example, an audio amplifier by mounting the transistors on the backside of the amplifier chassis. The chassis is exposed to the ambient outside the system and, therefore, is able to dissipate heat from the heat generating transistors to the outside ambient via the chassis. It would be useful to devise a similar scheme to computer systems to take advantage of the heat dissipation qualities of audio amplifiers. As will be seen, one embodiment of the present invention accomplishes this in a simple and elegant manner.
Conventional computer systems connect multiple processors through a bus network that provides communication among multiple processors, memory sub-systems, input/output sub-systems and other sub-systems. FIG. 5A is a general block diagram of such a configuration where microprocessors 500 are connected to the memory sub-system 502 and input/output sub-system 504 via connection stubs 506 to system bus 508. In this configuration, the bus stubs 506 allow each agent on the bus, e.g. processors, memory sub-systems, and input/output sub-systems, . . . etc., to drive the bus with a signal which is broadcasted to all of the agents sharing the bus 508 through bus stubs 506. Each agent receives every broadcasted signal, but only the agent waiting for the appropriate signal interprets the signal. Performance of such a configuration is greatly limited since the bus is at risk of being overloaded when the agents connected to the bus 508 become dedemanding, greatly degrading the performance.
Referring now to FIG. 5B, an alternative configuration of computer components is illustrated. Microprocessors 550, 552, 554 are shown connected in series along with memory system 556 and input/output subsystem 558 connected in series. Such a configuration typically requires a point-to-point interconnection in order for the components to communicate and to transfer information throughout the system. Many advantages are realized by such a configuration. Most importantly, the hand-shaking or point-to-point interconnect provides a mechanism to produce consistent signals with low degradation. Protocols used in such configurations are well known. Examples of such protocols can be found in related U.S. Pat. No. 5,546,023 of Borkar et al. Referenced above are, "Point-To-Point Phase-Tolerant Communication" of Self et al. and "A Microprocessor Point-to-Point Point Communication" of Self et al. cited above.
Removing the microprocessors and other VLSI chips away from their proximity to the other agents in such a configuration, for example, in order to move them to a different location, for cooling purposes, could greatly degrade their performance in the system. It would be useful, therefore, to devise a configuration that would allow the micro-processors and other VLSI chips to be moved out of the compact and warm environment and to allow exposure to other ambients providing better cooling for the VLSI chips. As will be seen in one embodiment, the present invention accomplishes this in a simple and elegant manner.